Method for producing a gate for a cmos transistor structure having a channel of reduced length

ABSTRACT

The invention relates to a process for making a gate for a CMOS transistor structure, made from a stack realized on a face in a semi-conducting material of a substrate, said stack comprising a gate isolation layer, a gate material layer and a gate mask in sequence, the process comprising the following steps:  
     a) anisotropic etching of the top part of the gate material layer not masked by the gate mask, this etching step leaving the bottom part of the gate material layer and leading to the formation of a deposit composed of etching products on the etching sides resulting from the anisotropic etching,  
     b) treatment of the deposit composed of etching products, to make a protection layer reinforced against subsequent etching of the gate material,  
     c) etching of the bottom part of the gate material layer as far as the gate isolation layer, this etching comprising isotropic etching of the gate material layer to make the gate shorter at the bottom than at the top.

TECHNICAL FIELD

[0001] The present invention relates to a process for making a gate fora short channel CMOS transistor structure.

STATE OF PRIOR ART

[0002] The polysilicon gate is the heart of a CMOS device. In atraditional approach, the gate is obtained by chaining aphotolithography step followed by an etching step. The photolithographystep defines the required dimension in a resin mask. The image obtainedin the resin is then transferred by plasma into a polysilicon oramorphous silicon layer, usually doped. This step is carried out in ahigh-density plasma etching reactor. The gate manufacturing step is ofprimary importance since the dimension of the gate fixes the deviceoperating speed. As a general rule, a deviation of the dimension up to10% of the target dimension is authorized. A special effort is made toobtain perfectly straight etching sides (anisotropic etching) during theetching step, such that the dimension of the polysilicon at the bottomof the gate is equal to the dimension of the polysilicon at the top ofthe gate, itself fixed by the mask dimension to the first order ofmagnitude. This is illustrated by FIG. 1 that shows a cross section ofpart of a CMOS transistor structure being made. A resin mask 1 (or ahard mask) enabled the formation of a gate 2 from a polysilicon,amorphous silicon or SiGe alloy layer deposited on a silicon substrate 3covered by a layer of gate oxide 4.

[0003] If the gate etching is anisotropic, the photolithography step isused to obtain the required gate dimension. This approach has been usedfor more than 40 years in microelectronics. Progress in lithography hasmade it possible to reduce the dimension of the transistor gates andtherefore to increase their operating speed.

[0004] This type of polysilicon gate may be etched by chaining severaldifferent etching steps, with the objective of obtaining straightetching sides to respect the dimension defined by the lithography stepas accurately as possible. The process usually comprises at least threesteps, each of which performs a very precise role.

[0005] The first step is a breakthrough step that eliminates the nativeoxide present on the surface of the polysilicon before etching. Thisstep is carried out under conditions which optimise elimination of thisnative oxide: high source power, strong polarization of the substrateholder. This step only lasts a few seconds since it is not veryselective with respect to the gate mask and therefore causes itsconsumption.

[0006] The second step, called the main etching step, quickly etches thepolysilicon and defines the etching anisotropy. It is generally donewith gas mixtures such as Cl₂/O₂, HBr/Cl₂/O₂ or HBr/O₂. The presence ofoxygen in the gas phase of the plasma enables the formation of silicon,oxygen and bromine or chlorine based etching products, depending onwhich mix is used. These etching products are deposited on the sides ofthe polysilicon while it is being etched. These non-volatile productsonly form when the energy of ions bombarding the substrate is greaterthan 70-80 eV. Therefore the polarization power applied to the substrateholder has to be adapted to the plasma density to enable the formationand atomisation of these etching products. The accumulation of etchingproducts deposited on the sides of the polysilicon generates apassivisation layer that protects the sides of the polysilicon fromspontaneous reactive chemical attack by neutral species of plasma(atomic chlorine or atomic bromine or excited atomic chlorine andbromine). For Cl₂/O₂, HBr/Cl₂/O₂ or HBr/O₂ type plasmas, surfaceanalyses by X photoelectron spectroscopy show that the passivisationlayer that forms during the main etching step is of theSiO_(x)Cl_(y)Br_(z) type, where x, y and z<1. It may be compared with aporous silicon oxide substoichiometric in oxygen but rich in bromine (inthe case of an HBr/O₂ chemistry) or in chlorine (in the case of a Cl₂/O₂chemistry). Its thickness is greater at the top of the gate (typicallybetween 5 and 10 nm) than at the bottom of the gate (of the order of 1to 2 nm). The thickness and the chemical composition of thepassivisation layer depend on the mix of the etching gases and operatingconditions of the plasma (RF power injected into the source, RFpolarisation power applied to the substrate holder, working pressure,etching gas flow).

[0007]FIG. 2 shows the formation of a passivisation layer while thepolysilicon layer is being etched. This figure shows the gate 2 in FIG.1 during manufacturing by etching a polysilicon layer 5. A passivisationlayer 7 is formed on the sides of the gate being formed under the actionof the ions 6 that bombard the polysilicon layer with sufficient energy.

[0008] The third step is the over-etching step. This eliminatespolysilicon residues that remain, if any, after the main etching step inthe dense lines of small polysilicon. Its duration is of the order of 30to 100% of the duration of the main etching step. During theover-etching step, the polarization power applied to the substrateholder is reduced to that applied during the main etching step(typically by a factor of 2) so as not to damage the gate oxide thatprotects the silicon substrate from structural and electrical damagethat could be caused by the plasma. During the over-etching step, thepassivisation layer is no longer supplied by etching products. Thepassivisation layer may then be eroded or completely etched by activespecies of the plasma (atomic chlorine, atomic bromine). In this case,the polysilicon is exposed to the active species. The resultingspontaneous etching reactions can cause severe distortions of theetching profiles. Therefore, in a standard etching process, if theanisotropy of the etching is to be perfect, the passivisation layerformed during the main etching step needs to be resistant enough so thatit is not fully consumed while it is exposed to the over etching plasma.

[0009] The main etching step may possibly be separated in two distinctsteps. A first step is identical to the step described previously. It isapplied during about the ⅔ or the ⅘ of the thickness of the polysiliconlayer. The RF polarization power applied to the substrate holder to etchthe remaining thickness of polysilicon is very much reduced, within arange of values identical to that applied during the over etching step,so that the gate oxide is reached under mild plasma (landing step)conditions in order to minimize its consumption.

[0010] Table I shows an example of the use of the etching process for aprocess comprising a main etching step in two parts (main etching I andmain etching II). In this example, it is considered that the plasma is ahigh-density inductive source capable of etching 200 mm substrates andthat the power injected in the source is of the order of 500 W. Theresult is that the plasma density is of the order of 10¹¹ ions/cm³. Thegas flows indicated and the working pressure are only given as examples.It is quite clear that the flows indicated for each gas can vary withina fairly wide range. The value of the RF power, called P, applied to thesubstrate holder in each step is only given for guidance. These valuesare different if the power injected in the source is different.

[0011] In this table, the gas flows are expressed in “sccm”, in otherwords in normal cm³/minute. The pressure is expressed in mTorr forpractical reasons (1 mTorr=approximately 0.133 Pa). TABLE I Chemistry ingaseous Gas flow Step phase Pressure P (W) Breakthrough C₂F₄ or Cl₂ 100sccm P > 200 a few mTorr Main etching I HBr/Cl₂/O₂ 150/30/5 sccm 80 < P< 150 a few mTorr Main etching II HBr/Cl₂/O₂ 150/30/5 sccm 40 < P < 70 afew mTorr Over-etching HBr/O₂ 150/10 sccm 40 < P < 60 > 30 mTorr

[0012] Recently, the specialized literature has started to includereferences to CMOS transistor structures with a notched gate bottom. Forexample, this is the case in article “100 nm Gate Length HighPerformance/Low Power CMOS Transistor Structure” by T. GHANI et al.published in the IEDM 1999 review, pages 415 to 418. Thus, a gate with abottom length shorter than the top length is obtained. This is shown inFIG. 3 in which, in comparison with FIG. 1, the reference 11 denotes themask, reference 12 denotes the gate, reference 13 denotes the substrateand reference 14 denotes the gate oxide layer. The effective electricallength of the gate is fixed by the intersection between polysilicon andthe gate oxide, and the final result is a gate with an effectivedimension less than the dimension fixed by the photolithography step.Therefore this configuration is attractive since it makes it possible togo beyond the resolution fixed by photolithography.

[0013] It may be assumed that the gate profile shown in FIG. 3 isobtained by means of etching that is anisotropic at first and thenbecomes strongly isotropic. One problem that can then arise is tocontrol lateral erosion at the bottom of the gate in order to obtain adetermined etching profile.

[0014] Patent U.S. Pat. No. 5,834,817 describes a field effecttransistor with a shaped gate electrode, this gate being shorter at thebottom than at the top. A stack is formed on one face made of a semiconducting material of a substrate, the stack comprising a gateisolation layer, a gate material layer and a gate mask in sequence. Theprocess includes the following steps:

[0015] anisotropic etching of the top part of the layer of gate materialnot masked by the gate mask, this etching step leaving the bottom partof the layer of gate material and leading to the formation of a depositcomposed of etching products, on the etching sides resulting from theanisotropic etching,

[0016] etching of the bottom part of the gate material layer as far asthe gate isolation layer, this etching comprising isotropic etching ofthe layer of gate material to make the gate shorter at the bottom thanat the top.

SUMMARY OF THE INVENTION

[0017] The present invention proposes to machine the passivisation layerthat is formed during etching of the gate to give it an anisotropicetching profile at its top and a very sharply isotropic profile at thebottom of the gate.

[0018] The purpose of the invention is a process for making a gate for aCMOS transistor structure for which the gate length is shorter at thebottom than at the top, made from a stack realized on a face in asemi-conducting material of a substrate, said stack comprising a gateisolation layer, a gate material layer and a gate mask in sequence, theprocess comprising the following steps:

[0019] a) anisotropic etching of the top part of the gate material layernot masked by the gate mask, this etching step leaving the bottom partof the gate material layer and leading to the formation of a depositcomposed of etching products on the etching sides resulting from theanisotropic etching,

[0020] c) etching of the bottom part of the gate material layer as faras the gate isolation layer, this etching comprising isotropic etchingof the gate material layer to make to the gate a length shorter at thebottom than at the top,

[0021] characterised in that there is a step b) between steps a) and c),for the treatment of the deposit composed of etching products, to make aprotection layer reinforced against etching in step c).

[0022] The surface of the lower part of the gate material layer may besubjected to a cleaning step after step b) and before step c).

[0023] According to a first embodiment, step c) comprises two sub-steps:

[0024] firstly, an anisotropic etching step of the lower part of thegate material layer as far as the gate isolation layer,

[0025] then a step consisting of submitting the stack to an over-etchingplasma that causes said isotropic etching.

[0026] According to a second embodiment, step c) is made up by applyingan over etching plasma to the stack to reach the gate isolation layerand to make to said gate a length shorter at the bottom than at the top.

[0027] The isotropic etching of the gate material layer may be doneusing reactive species reacting with the gate material in the absence ofplasma.

[0028] According to one particular example embodiment, the depositcomposed of etching products being of the SiO_(x)Cl_(y)Br_(z) type wherex, y and z<1 and y or z possibly being equal to 0, step b) consists ofsubstituting the chlorine and/or bromine in the deposit composed ofetching products, by oxygen. In this case, the substitution of thechlorine and/or bromine may be done by means of a gas plasma comprisingat least one gas based on oxygen. The gas based on oxygen may be chosenfrom among O₂, O₃, H₂O, N₂O, NO, CO, CO₂, SO₂ or SO₃. The gas plasma mayalso comprise at least one gas chosen from among Ar, Xe, Kr, NH₃ and N₂.In this case, step b) can advantageously take place after the substratehas been placed on an unpolarised substrate: holder.

[0029] According to another example of a particular embodiment, in stepb), treatment of the deposit composed of etching products consists ofdepositing a polymer layer on said deposit composed of etching products.Treatment of the deposit composed of etching products may consist ofdepositing a layer of fluorocarbonated polymer, for example by using aC_(x)F_(y)H_(z) type plasma. In this case, step b) preferably takesplace after placing the substrate on a polarized substrate holder toprevent the deposit of a polymer layer on the surface of the lower partof the layer of gate material and to prevent etching of this surface.

[0030] The invention is particularly applicable to making a gate from asilicon-based material.

[0031] It is also applicable to making a metallic type gate, the layerof gate material comprising a sub-layer based on a semi-conductingmaterial forming the top part of the gate material layer and a metallicsub-layer forming the lower part of the gate material layer.

BRIEF DESCRIPTION OF THE DRAWINGS

[0032] The invention will be better understood and other advantages andspecificities will become clear after reading the following descriptiongiven as a non-limitative example, accompanied by the appended drawings,wherein:

[0033]FIG. 1, already described, shows a cross section showing part of aCMOS transistor structure during manufacture, according to the priorart,

[0034]FIG. 2, already described, shows the formation of a passivisationlayer during an etching step of a gate material layer according to theprior art,

[0035]FIG. 3, already described, shows a cross section through part of aCMOS transistor structure according to a recent proposal of the priorart,

[0036]FIGS. 4A to 4D are cross sectional views illustrating steps in aprocess for making a CMOS transistor structure according to theinvention,

[0037]FIGS. 5A to 5C are cross sectional views illustrating steps in aprocess for making a second CMOS transistor structure according to theinvention.

DETAILED DESCRIPTION OF EMBODIMENTS OF THE INVENTION

[0038] We will now describe how to make a first CMOS transistorstructure according to the invention, with relation to FIGS. 4A to 4D.

[0039]FIG. 4A shows a silicon substrate 20 supporting a silicon oxidelayer 21, a gate of material layer 22 (for example polysilicon oramorphous silicon) and then a resin mask 23 in sequence. This figureshows the state of the structure during the anisotropic etching step ofthe top part of the gate material layer 22. A deposit 24 (orpassivisation layer) composed of etching products is formed on the sidesof the gate while it is being made. If the etching plasma 25 is anHBr/Cl₂/O₂ plasma, the deposit 24 is of the SiO_(x)Cl_(y)Br_(z) typewhere x, y and z<1. This passivisation layer 24 protects the sides ofthe gate during etching. It is thicker at the top than at the bottom ofthe gate and it has a certain porosity and substoichiometry in oxygen,that weakens it. The layer 24 is formed at a depth Ed by depositingetching products on the sides of the gate being created. For example,the etching step in which this layer is created may be the main etchingstep I in table I.

[0040] The passivisation layer 24 may be reinforced by exposure to anoxygen-based plasma 26 (see FIG. 4B). This exposure substitutes oxygenfor the chlorine and bromine present in layer 24. This step transformsthe passivisation layer into a protection layer 27 composed of anSiO_(x) type material denser than the original layer and therefore moreresistant to a subsequent etching step.

[0041] Gas mixes for reinforcing the passivisation layer by oxidizing itare oxygen based mixes. The O₂, O₃, H₂O, N₂O, NO, CO, CO₂, SO₂, SO₃gases can be used to perform this operation. These gases may be mixedwith neutral gases such as Ar, Xe, Kr and NH₃ or N₂ type gases. In orderto oxidise the passivisation layer, a strongly dissociated high-densityplasma generates strong concentrations of atomic oxygen in the gaseousphase. Oxidisation of the passivisation layer is more efficient when thepower injected in the plasma is high. This technique has thedisadvantage that it oxidises the surface of the gate material (oxidelayer 28) that remains to be etched, which will necessitate abreakthrough step in the remainder of the process. To minimizeoxidisation of the surface of the gate material, polarisation must notbe applied to the substrate holder during oxidation of the passivisationlayer.

[0042] Another solution for reinforcing the passivisation layer consistsof exposing the layer to a C_(x)F_(y)H_(z) plasma to deposit a layer offluorocarbonated polymer on the etching sides. All C_(x)F_(y)H_(z) typegases used for etching SiO₂ can be used, including C₂F₆, C₄F₈, C₂F₁,C₃F₆, CHF₃, CH₃F, etc. In the case of a C_(x)F_(y)H_(z) plasma, it isimportant to avoid deposition of a polymer film on the surface of thegate material 22. To achieve this, the substrate holder that supportsthe substrate 20 is polarized so as to avoid the deposit of a polymer onthis surface and so as to not etch the gate material. The polarisationpower RF applied to minimize consumption of the gate material depends onthe plasma density (therefore the RF power injected in the source) andthe nature of the C_(x)F_(y)H_(z) gas.

[0043] Two approaches can be considered to continue the process.

[0044] A first approach consists of continuing anisotropic etching ofthe layer of gate material 22 as far as the gate isolation layer 21.This is as shown in FIG. 4C. The oxide layer 28 (see FIG. 4B) that wasformed during production of the protection layer 27 if the passivisationlayer was reinforced by oxygen, was eliminated in a previousbreakthrough step. If the passivisation layer was reinforced by apolymer deposit, the breakthrough step eliminates the polymer formed onthe surface of the layer of gate material 22. This breakthrough step isfollowed by an anisotropic etching step of the layer of gate material asfar as the gate isolation layer 21 due to the same plasma 25 used toetch the top part of the layer of gate material. The result is theformation of another passivisation layer 29 on the sides of the gate 30thus delimited. This layer 29 is superposed on the protection layer 27at the top part of the gate 30. Particular plasma conditions preventformation of the passivisation layer 29 by eliminating oxygen andbromine from the plasma gas phase.

[0045] The gate 30 is then exposed to an over-etching plasma 31 so thatthe gate is machined laterally at the location at which thepassivisation layer 29 is not reinforced (see FIG. 4D). The duration ofthis step adjusts the amplitude of the lateral etching (isotropicetching) without disturbing the anisotropy of the profile over theentire thickness in which the passivisation layer was reinforced.Therefore, the duration of this step will be used to check the length CDof the bottom of the gate. The over-etching step is perfectly selectivecompared with the gate isolation layer 21. It is also perfectlyselective compared with the protection layer 27 formed on the sides ofthe gate 30.

[0046] A second approach consists of performing the over-etching stepimmediately when the passivisation layer has been reinforced and thebreakthrough step has been done, to begin controlled lateral erosion atthe bottom of the gate. Thus, the step shown in FIG. 4B is directlyfollowed by the step shown in FIG. 4D. This approach has the importantadvantage that the gate isolation layer is reached under very mildplasma operating conditions. However, the final check of the length CDof the bottom of the gate is more difficult with this method, since thefinal length is controlled by the ratio between the vertical and lateraletching speeds of the gate material. On the other hand, with the firstapproach, only the etching speed affects control over the length CD.Furthermore, the effects of loads can modify the lateral erosion ratewhen the gate material is completely exposed on the gate isolation.Nevertheless, this approach is still a realistic way of reducing thesize of the gate with respect to the dimension defined by thelithography step.

[0047] Table II contains an example embodiment of the process accordingto the invention for a silicon substrate supporting a gate oxide layermade of polysilicon. This example relates to the first approach with apassivisation layer reinforced by an oxygen-based plasma. In thisexample, it is considered that the plasma is a high-density inductivesource that etches 200 mm substrates and that the power injected in thesource is of the order of 500 W. The result is that the plasma densityis of the order of 10¹¹ ions/cm³. Gas flows and the working pressuresindicated are only given as examples. Flows indicated for each gas canvary within a fairly wide range. The value of the RF power applied tothe substrate holder at each step is only given for guidance. Thesevalues are different if the power injected in the source is different.TABLE II Chemistry in gaseous Gas flow Step phase Pressure P (W)Breakthrough C₂F₄ or Cl₂ 100 sccm 150 < P < 200 a few mTorr Main etchingI HBr/Cl₂/O₂ 150/30/5 sccm 80 < P < 150 a few mTorr Reinforcement O2 150sccm P = 0 > 15 mTorr Breakthrough Cl₂ 100 sccm 150 < P < 200 a fewmTorr Main etching II HBr/Cl₂/O₂ 150/30/5 sccm 50 < P < 80 a few mTorrOver-etching HBr/O₂ 150/10 sccm 40 < P < 60 > 30 mTorr

[0048] Reactive gases can also be used that, in the absence of a plasma,can react spontaneously with the gate material to cause lateral erosionat the bottom of the gate.

[0049] As a general rule, plasma helps to produce chemically active andelectric reactive species (ions and electrons) that participate inetching. The anisotropy of etching results from the synergy between ionsand neutral species of the plasma, ionic bombardment significantlyaccelerating the chemical etching dynamics due to the neutral species.During lateral etching of the bottom of the gate, lateral erosion of thegate material occurs by neutral species of the plasma that reactspontaneously with the gate material to form volatile reaction products.Plasma ions do not play any role in this lateral chemical attack sincethey arrive vertically and not directly on the sides of the gate thatare eroded by neutral species.

[0050] During this lateral etching step, the process may be complicatedby ionic and electronic bombardment due to the plasma. It is importantto avoid damaging the gate isolation layer that is bombarded byhigh-energy plasma ions during the lateral erosion step of the bottom ofthe gate. The selectivity of etching between the gate material and thegate isolation can then become too weak to prevent damage to futureactive zones of the transistor. Furthermore, the electric field of theplasma may be sufficiently high so that plasma ions are directlyimplanted into the substrate through the gate isolation layer, duringthis lateral erosion step. Finally, the difference in direction betweenthe plasma ions and electrons can produce charge effects provokingelectron currents in the gate isolation layer during execution of theprocess and may cause degradation of this insulation. The result is thatthere are definite advantages in having a lateral erosion step of thegate in the absence of a plasma.

[0051] Therefore, isotropic etching of the layer of the gate materialmay be done using reactive species reacting with the gate material inthe absence of a plasma.

[0052] Fluorine based gases are very attractive candidates for isotropicetching of a silicon based material gate (amorphous or polysilicon), thegate isolation layer being made of silicon oxide. At ambienttemperature, the ratio of the etching rates of silicon and silicon oxideby atomic fluorine is 44. At 100° C., this ratio is equal to 25.Therefore it is particularly useful to be able to produce a source ofatomic fluorine in the absence of a plasma since spontaneous etching ofsilicon becomes possible without any consumption of the gate oxide. Thislateral etching erodes the silicon on the sides of the gate withoutconsuming the gate oxide and without any risk of creating structural orelectrical defects in the silicon. Therefore in order to achieve this,it is necessary to select gases which dissociate spontaneously in theabsence of a plasma at the silicon surface to produce a source of atomicfluorine. Gases such as XeF₂ and F₂ are good candidates since thesegases efficiently etch silicon in the absence of a plasma.

[0053] Furthermore, since the lateral erosion rate depends on thepartial pressure of the gas (XeF₂ or F₂) in the reactor and thesubstrate temperature, the lateral erosion rate and therefore the finaldimension at the bottom of the gate can be controlled extremelyprecisely to obtain etching profiles of the type shown in FIG. 4D.

[0054] The invention is also applicable to cases of structures with ametallic gate. Metallic gates are potentially interesting formicroelectronic industries of the future. However, they have thedisadvantage that it is very difficult to include them in technologicalindustries. The etching step is particularly difficult to implementsince the etching anisotropy and integrity of the gate oxide are verydifficult to reconcile for metals. However, the invention isparticularly interesting in the case of a layer of gate materialcomposed of a stack of semi-conducting materials on metal.

[0055]FIGS. 5A to 5C illustrate application of the invention to the caseof a metallic gate.

[0056]FIG. 5A shows a silicon substrate 40 supporting a silicon oxidelayer 41, a layer of gate material 50 and a resin mask 42 in sequence.The layer of gate material 50 comprises a lower metallic sub-layer 51,for example made of Al, W or TiN, and an upper sub-layer 52, for examplemade of polysilicon or amorphous silicon. FIG. 5A shows the state of thestructure during the anisotropic etching step of the upper sub-layer 52by a plasma 43. A deposit 44 composed of etching products is formed onthe sides of the gate being produced. The etching plasma 43 may forexample be of the HBr/Cl₂/O₂ type.

[0057] As above, the passivisation layer is reinforced using anoxygen-based plasma 45 to supply a protection layer 46 (see FIG. 5B). Aspreviously, the passivisation layer may be reinforced by afluorocarbonated polymer. FIG. 5B shows that the oxygen-based plasma hasoxidised the surface of the metallic sub-layer 51 to produce an oxidelayer 47.

[0058] After a step to breakthrough the oxide layer 47, the metallicsub-layer 51 is etched using an etching plasma 48 that causes isotropicetching while preserving the layer of gate oxide 41. The duration ofthis step is sufficient to obtain the required dimension at the bottomof the gate. This approach is particularly suitable for metallic gatessince these materials are naturally etched isotropically. A gate 49 isobtained comprising a metallic lower part and an upper part made of asemi-conducting material.

1. Process for making a gate (30, 49) for a CMOS transistor structurefor which the gate length is shorter at the bottom than at the top, madefrom a stack realized on a face in a semi-conducting material of asubstrate (20, 40), said stack comprising a gate isolation layer (21,41), a gate material layer (22, 51, 52) and a gate mask (23, 42) insequence, the process comprising the following steps: a) anisotropicetching of the top part of the gate material layer not masked by thegate mask (23, 42), this etching step leaving the bottom part of thegate material layer and leading to the formation of a deposit (24, 44)composed of etching products on the etching sides resulting from theanisotropic etching, c) etching of the bottom part of the gate materiallayer (21, 41) as far as the gate isolation layer, this etchingcomprising isotropic etching of the gate material layer to make to thegate (30, 49) a length shorter at the bottom than at the top,characterised in that there is a step b) between steps a) and c), forthe treatment of the deposit (24, 44) composed of etching products, tomake a protection layer (27, 46) reinforced against etching in step c).2. Process according to claim 1, characterised in that step c) comprisestwo sub-steps: firstly, an anisotropic etching step of the lower part ofthe gate material layer as far as the gate isolation layer, then a stepconsisting of submitting the stack to an over-etching plasma that causessaid isotropic etching.
 3. Process according to claim 1, characterisedin that step c) consists of applying an over etching plasma (31) to thestack to reach the gate isolation layer (21) and to make to said gate(30) a length shorter at the bottom than at the top.
 4. Processaccording to claim 1, characterised in that the isotropic etching of thegate material layer is done using reactive species reacting with thegate material in the absence of a plasma.
 5. Process according to anyone of claims 1 to 4, characterised in that the deposit (24, 44)composed of etching products being of the SiO_(x)Cl_(y)Br_(z) type wherex, y and z<1 and y or z possibly being equal to 0, step b) consists ofsubstituting the chlorine and/or bromine in the deposit composed ofetching products, by oxygen.
 6. Process according to claim 5,characterised in that the substitution of the chlorine and/or bromine isdone by means of a gas plasma comprising at least one gas based onoxygen.
 7. Process according to claim 6, characterised in that the gasbased on oxygen is chosen from among O₂, O₃, H₂O, N₂O, NO, CO, CO₂, SO₂or SO₃.
 8. Process according to either of claims 6 or 7, characterisedin that the gas plasma also comprises at least one gas chosen from amongAr, Xe, Kr, NH₃ and N₂.
 9. Process according to any one of claims 1 to4, characterised in that during step b), the treatment of the depositcomposed of etching products consists of depositing a polymer layer onsaid deposit composed of etching products.
 10. Process according toclaim 9, characterised in that the treatment of the deposit composed ofetching products consists of depositing a layer of fluorocarbonatedpolymer.
 11. Process according to claim 10, characterised in that thelayer of fluorocarbonated polymer is deposited using a C_(x)F_(y)H_(z)type plasma.
 12. Process according to claim 10, characterised in thatstep b) takes place after placing the substrate on a polarized substrateholder to prevent the deposit of a polymer layer on the surface of thelower part of the layer of gate material and to prevent etching of thissurface.
 13. Application of the process according to any one of claims 1to 12, for making a gate (30) from a silicon-based material. 14.Application of the process according to any one of claims 1 to 12, formaking a metallic type gate (49), the layer of gate material (50)comprising a sub-layer based on a semi-conducting material (52) formingthe upper part of the gate material layer and a metallic sub-layer (51)forming the lower part of the gate material layer.